Today I challenged myself with a circuit design task. Using the parts I had at my workbench, I wanted to make a device that could accurately keep time. I also recently discovered people were making “binary clocks” and thought it would be cool to build it. Originally, my plan was to use a 32.768kHz crystal and use lots of JK flip flops to divide it’s frequency by 2 and eventually get a frequency of 1Hz, but I realized quickly that I’d need way too many (15 to be exact) and I only had 4 to use for the entire project. I decided to use a 4 pin crystal oscillator instead, but I was also able to use a 4MHz, 2 pin crystal wired to a transistor to produce an oscillation.
I chose a 1MHz oscillator because I had it around from previous AM radio experiments. However, 1MHz can’t be divided by 2 to get 1Hz. I realized it had to be divided by powers of 10. Thankfully, I discovered I had binary counters lying around that just happened to count to 10. I used 6 of them in series to divide my frequency by a total factor of 10^6, or 1000000, so my final output frequency was 1Hz.
For the seconds counter, I decided to cheat a little to save on my flip flop usage, and used an LED bar graph I had lying around with a 4017 decade counter. This was pretty simple to wire up because I’ve used it in the past; I connected the 1Hz signal to the clock in pin, and the carry out pin connects to the next stage of the circuit (0.1Hz).
The next stage of the circuit is where I implemented the JK flip flops (3 of them). Since the tens digit in seconds needs to only count to 5, I was able to get away with 3 LED’s (which shows binary from 0-7). I wired J and K to +5V, and the clock in pin to the 0.1Hz signal from the 4017.
Something I learned while building this circuit is that the succesive JK flip flop needs to be connected to !Q, instead of Q of the previous flip flop, for the binary sequence to count correctly. To show why, here is part of the binary sequence for 3 bits:
Bit 2 Bit 1 Bit 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
Notice how bit 1 only toggles when bit 0 changes states from 1-0. This can be called that bit’s falling edge. Since the 4027 JK flip flop toggles Q on the rising edge of the clock signal input, then the wire connecting it to the previous flip flop must be inverted. Instead of using a dedicated IC, why not just use the !Q pin, which is already on the 4027 IC to save parts.
Since the circuit right now will count the tens digit up to 7 then reset to 0, I needed to make another module that would reset all the flip flops when the count goes past 5. I thought this would be easy, since 6 in binary is 1 1 0, and I could just put an AND gate connecting to bit 2 and bit 1, connect it’s output to the clear pin on each flip flop, and everything would work. However, when transitioning from 0 1 1 to 1 0 0, all 3 outputs are on for a brief period of time, which causes the AND gate to false trigger and the second counter never gets past 39. I realized that I had to make another circuit that would reject false triggers from the AND gate, and allow the real ones to pass through.
I was able to come up with this:
![mini-diagram](https://wselectronicsblog.wordpress.com/wp-content/uploads/2017/02/mini-diagram1.png?w=625)
I configured the 555 to operate in monostable mode, meaning it won’t oscillate, but when the trigger pin goes high, it will output a single pulse for a set period of time (determined by the RC constant), then go low and stay low. I thought I could fine tune the length of this pulse to be just a tiny bit longer than the false trigger coming from the AND gate, but short enough so that it doesn’t create a noticeable delay for humans to see. Using a comparator, I connected the 555’s output pulse into the inverting input of the comparator and the output of the AND gate to the non-inverting input through a voltage divider.
When the AND gate false triggers, it will send a signal to the trigger pin of the 555, causing it to go high, as well as a signal to the non-inverting input of the comparator. Since the non-inverting input’s voltage will be less than the inverting input (because of the voltage divider), the comparator will remain off. During a false trigger, the AND gate’s output will turn off long before the 555 pulse goes low, so the inverting input of the comparator will remain high while the non-inverting input will go back low again. This keeps the comparator in the off state.
However, when the AND gate false triggers, the 555’s pulse will turn off before the AND gate’s output does (since the AND gate will remain on for 20 seconds unless it’s reset!). This causes the inverting input of the comparator to go low, but the non-inverting input is still high because of the AND gate, so the output of the comparator finally goes high. The output is connected to the clear pins of Bit 2 and Bit 1 (Bit 0 doesn’t need it because it goes to 0 automatically for 6 as well), so the counter resets itself to 0 and counts up to 5 again.
Overall, this creates a circuit that can count from 0-59 seconds. Obviously this circuit could be duplicated so that it could be a little more useful and count up to an hour of time. I just didn’t want to make it because it’s a lot of wiring for a breadboard!
Here is the overall schematic (I have boxed in each section to make each part easier to understand):
![overall.PNG](https://wselectronicsblog.wordpress.com/wp-content/uploads/2017/02/overall1.png?w=625)
Here is what I made on the breadboard:
![img_20170204_0812026611](https://wselectronicsblog.wordpress.com/wp-content/uploads/2017/02/img_20170204_0812026611.jpg?w=625)
The full working circuit using the 1MHz crystal as a clock input.
![img_20170204_0811548522](https://wselectronicsblog.wordpress.com/wp-content/uploads/2017/02/img_20170204_0811548522.jpg?w=625)
Proof that I can use a regular 2 pin crystal for a wider range of frequencies.